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Flash ADC architecture

Stojcevski, Aleksandar and Le, Hai Phuong and Singh, J and Zayegh, Aladin (2003) Flash ADC architecture. Electronics letters, 39 (6). pp. 501-502. ISSN 0013-5194

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Abstract

A 4-bit, 2.5 V modified flash analogue-to-digital converter (ADC) has been designed. In this design, the new flash topology only requires 2/sup (N-2)/+2 comparators. For comparison reasons, this new ADC architecture is operated at 400 MHz, consumes a total power of 1.68 mW and generates a total noise power of 4.86/spl times/10/sup -15/. /spl Delta/f(V/sup 2/) at this frequency.

Item Type: Article
Uncontrolled Keywords: analogue-digital conversion, comparators (circuits), integrated circuit noise, 1.68 mW, 2.5 V, 4 bit, 400 MHz, ADC, comparators, flash analogue-to-digital converter, flash topology, high-speed converter, total noise power, total power
Subjects: RFCD Classification > 290000 Engineering and Technology
Faculty/School/Research Centre/Department > School of Engineering and Science
Depositing User: Ms Phung T Tran
Date Deposited: 20 Oct 2008 04:12
Last Modified: 18 Mar 2015 03:33
URI: http://vuir.vu.edu.au/id/eprint/1090
DOI: 10.1049/el:20030290
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Citations in Scopus: 16 - View on Scopus

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