Performance analysis of optimised CMOS comparator
Le, Hai Phuong and Zayegh, Aladin and Singh, J (2003) Performance analysis of optimised CMOS comparator. Electronics letters, 39 (11). pp. 833-835. ISSN 0013-5194Full text for this resource is not available from the Research Repository.
A high-speed low-power latched CMOS comparator circuit is presented. Demonstrated is a circuit optimisation technique to obtain minimum offset error at 500 MHz sampling speed. Also, a mathematical model representing the noise in the device is developed. After optimisation, the comparator achieved 10-bit resolution on a 1 V differential input at 500 MHz speed and had a noise figure of 4.747 dB at this frequency.
|Uncontrolled Keywords:||CMOS analogue integrated circuits, circuit optimisation, comparators (circuits), integrated circuit noise, low-power electronics, 1 V, 4.747 dB, 500 MHz, circuit optimisation technique, comparator, differential input, low-power latched comparator circuit, mathematical model, minimum offset error, noise figure, optimised CMOS comparator, sampling speed|
|Subjects:||RFCD Classification > 290000 Engineering and Technology
Faculty/School/Research Centre/Department > School of Engineering and Science
|Depositing User:||Ms Phung T Tran|
|Date Deposited:||20 Oct 2008 05:05|
|Last Modified:||18 Mar 2015 03:32|
|ePrint Statistics:||View download statistics for this item|
|Citations in Scopus:||14 - View on Scopus|
Repository staff only