Research Repository

Unbiased Finite-Memory Digital Phase-Locked Loop

You, SH, Pak, JM, Ahn, CK, Shi, Peng ORCID: 0000-0001-8218-586X and Lim, MT (2016) Unbiased Finite-Memory Digital Phase-Locked Loop. IEEE Transactions on Circuits and Systems II: Express Briefs, 63 (8). 798 - 802. ISSN 1549-7747

Full text for this resource is not available from the Research Repository.
Item Type: Article
Uncontrolled Keywords: DPLLs; UFMDPLL; incorrect noise information; signal processing; control; signals
Subjects: FOR Classification > 0906 Electrical and Electronic Engineering
Faculty/School/Research Centre/Department > College of Science and Engineering
Depositing User: Symplectic Elements
Date Deposited: 06 Apr 2017 23:52
Last Modified: 19 Sep 2019 23:33
URI: http://vuir.vu.edu.au/id/eprint/33066
DOI: https://doi.org/10.1109/TCSII.2016.2531138
ePrint Statistics: View download statistics for this item
Citations in Scopus: 18 - View on Scopus

Repository staff only

View Item View Item

Search Google Scholar