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Improving IEEE 1588v2 Time Synchronization Performance With Phase Locked Loop

Jahja, RH, Dahal, Saurav ORCID: 0000-0002-8918-2036, Suk-Seung, H, Goo-Rak, K, Pyun, JY and Shin, S (2014) Improving IEEE 1588v2 Time Synchronization Performance With Phase Locked Loop. In: 2014 48th Asilomar Conference on Signals, Systems and Computers, 02 November 2014-05 November 2014, Pacific Grove, California.

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Item Type: Conference or Workshop Item (Paper)
ISBN: 9781479982974
Uncontrolled Keywords: clock synchronization protocol; phase locked loop; clock accuracy; synchronization algorithm
Subjects: FOR Classification > 0803 Computer Software
Faculty/School/Research Centre/Department > College of Science and Engineering
Depositing User: Symplectic Elements
Date Deposited: 20 Nov 2018 22:19
Last Modified: 20 Nov 2018 22:19
URI: http://vuir.vu.edu.au/id/eprint/37491
DOI: https://doi.org/10.1109/ACSSC.2014.7094439
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Citations in Scopus: 0 - View on Scopus

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