Improving IEEE 1588v2 Time Synchronization Performance With Phase Locked Loop

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Jahja, RH, Dahal, Saurav ORCID: 0000-0002-8918-2036, Suk-Seung, H, Goo-Rak, K, Pyun, JY and Shin, S (2014) Improving IEEE 1588v2 Time Synchronization Performance With Phase Locked Loop. In: 2014 48th Asilomar Conference on Signals, Systems and Computers, 02 November 2014-05 November 2014, Pacific Grove, California.

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Item type Conference or Workshop Item (Paper)
URI http://vuir.vu.edu.au/id/eprint/37491
DOI https://doi.org/10.1109/ACSSC.2014.7094439
Official URL https://ieeexplore.ieee.org/document/7094439
ISBN 9781479982974
Subjects Current > FOR Classification > 0803 Computer Software
Current > Division/Research > College of Science and Engineering
Keywords clock synchronization protocol; phase locked loop; clock accuracy; synchronization algorithm
Citations in Scopus 2 - View on Scopus
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