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Design and Implementation of High Power, High Linearity Stacked RF FET Switches in a 250 nm Silicon on Sapphire Process

Pourakbar, Mohammadreza, Redouté, Jean-Michel and Faulkner, Michael (2011) Design and Implementation of High Power, High Linearity Stacked RF FET Switches in a 250 nm Silicon on Sapphire Process. In: Asia-Pacific Microwave Conference 2011 (APMC 2011). Engineers Australia, Barton, A.C.T, pp. 299-302.

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Abstract

The RF circuitry in new generation mobile handsets is continuously becoming smaller while containing more functionality. Silicon-on-sapphire (SOS) technology is an advanced active device process that eases the fabrication of advanced wireless components on very high resistivity substrates. This paper presents the basic theory and resulting trade-offs regarding RF FET switches in order to achieve a high power handling capability, low insertion loss and high linearity of the latter. A combined RF switch consisting of eight stacked FETs, used in a high power switched capacitor banks, is designed with an insertion loss of 1 dB at 2 GHz for a transmitter power of 39.5 dBm. The presented configuration has a high linearity featuring P1dB and IIP3 of 49.2 dBm and 54.3 dBm, respectively.

Item Type: Book Section
ISBN: 9780858259744 (CD-ROM)
Additional Information:

Conference was held from 5th - 8th December 2011 at Melbourne Convention and Exhibition Centre, Australia

Uncontrolled Keywords: ResPubID23605, integrated circuit design, high power, radio frequency (RF), switch, silicon-on-sapphire, switched-capacitor bank
Subjects: Faculty/School/Research Centre/Department > Centre for Telecommunications and Micro-Electronics (CTME)
FOR Classification > 0906 Electrical and Electronic Engineering
SEO Classification > 8617 Communication Equipment
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Depositing User: VUIR
Date Deposited: 22 Mar 2013 05:54
Last Modified: 22 Mar 2013 05:54
URI: http://vuir.vu.edu.au/id/eprint/9593
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Citations in Scopus: 2 - View on Scopus

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