Performance analysis of optimised CMOS comparator

Full text for this resource is not available from the Research Repository.

Le, Hai Phuong, Zayegh, Aladin and Singh, J (2003) Performance analysis of optimised CMOS comparator. Electronics letters, 39 (11). pp. 833-835. ISSN 0013-5194

Abstract

A high-speed low-power latched CMOS comparator circuit is presented. Demonstrated is a circuit optimisation technique to obtain minimum offset error at 500 MHz sampling speed. Also, a mathematical model representing the noise in the device is developed. After optimisation, the comparator achieved 10-bit resolution on a 1 V differential input at 500 MHz speed and had a noise figure of 4.747 dB at this frequency.

Dimensions Badge

Altmetric Badge

Item type Article
URI https://vuir.vu.edu.au/id/eprint/1093
DOI https://doi.org/10.1049/el:20030546
Official URL http://dx.doi.org/10.1049/el:20030546
Subjects Historical > RFCD Classification > 290000 Engineering and Technology
Historical > Faculty/School/Research Centre/Department > School of Engineering and Science
Keywords CMOS analogue integrated circuits, circuit optimisation, comparators (circuits), integrated circuit noise, low-power electronics, 1 V, 4.747 dB, 500 MHz, circuit optimisation technique, comparator, differential input, low-power latched comparator circuit, mathematical model, minimum offset error, noise figure, optimised CMOS comparator, sampling speed
Citations in Scopus 23 - View on Scopus
Download/View statistics View download statistics for this item

Search Google Scholar

Repository staff login