Eslampanah, Raheleh (2016) Adaptive Duplexer Control for Wireless Transceivers. PhD thesis, Victoria University.

Abstract

The popularity of smart phones, cloud computing and the growing market for machineto- machine communications is fuelling the growth of mobile broadband. More frequency bands are therefore being allocated to mobile services. Unfortunately, for historical reasons, these band allocations are fragmented, poorly harmonised between different countries and no longer large enough for the ever-increasing broadband data rates. Carrier aggregation, the operation on two or more bands at once, will be necessary. A future wireless terminal capable of global roaming would therefore have to handle 35 bands, and be capable of carrier aggregation. This is the research challenge. Duplexing is a technique to simultaneously transmit and receive information from the same antenna. Frequency Division Duplex uses two frequency bands for uplink and downlink communications, enabling the transmitter and receiver to operate continuously. Duplexing filters are essential for isolating the receiver from the strong self transmitted signal. Unfortunately the filters are expensive, non tunable and not suitable for integration into silicon. Each new frequency band requires its own duplexing filter and a complex array of switches and filters is required for multi-band operation This work presents an adaptive duplexer architecture compatible with silicon integration. It is tunable over a wide frequency range and capable of carrier aggregation. The structure uses a combination of a low isolation device with multiple analog cancelling loops controlled by a normalised least mean square algorithm to track changes in signal leakage. The control is a multi-input multi-output problem. However the use of the ”inverse plant control technique” enables orthogonalisation into multi single-input single-output problems, simplifying the structure and reducing convergence time over previous search algorithms. Convergence takes 10ms from ’cold’ and tracking has a latency of 1.5ms. Low power pseudo noise pilot signals placed in the receive bands measure the cancelling error residues used as feedback to the controller. The pilot generator is integrated into silicon using the Peregrine UltraCMOSr GC process. The generator was programmable to four sequence lengths and 8 delays for correlation purposes. The maximum chip rate of 100Mchip/s was more than the 10Mchip/s required for an LTE channel.

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