Unbiased Finite-Memory Digital Phase-Locked Loop
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You, Sung Hyun, Pak, Jung Min, Ahn, Choon Ki ORCID: 0000-0003-0993-9658 (external link), Shi, Peng ORCID: 0000-0001-8218-586X (external link) and Lim, Myo Taeg (2016) Unbiased Finite-Memory Digital Phase-Locked Loop. IEEE Transactions on Circuits and Systems II: Express Briefs, 63 (8). 798 - 802. ISSN 1549-7747
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Item type | Article |
URI | https://vuir.vu.edu.au/id/eprint/33066 |
DOI | 10.1109/TCSII.2016.2531138 (external link) |
Official URL | http://ieeexplore.ieee.org/document/7410011/ (external link) |
Subjects | Historical > FOR Classification > 0906 Electrical and Electronic Engineering Current > Division/Research > College of Science and Engineering |
Keywords | DPLLs; UFMDPLL; incorrect noise information; signal processing; control; signals |
Citations in Scopus | 24 - View on Scopus (external link) |
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