Unbiased Finite-Memory Digital Phase-Locked Loop

Download
Full text for this resource is not available from the Research Repository.
Export

You, SH, Pak, JM, Ahn, CK, Shi, Peng ORCID: 0000-0001-8218-586X and Lim, MT (2016) Unbiased Finite-Memory Digital Phase-Locked Loop. IEEE Transactions on Circuits and Systems II: Express Briefs, 63 (8). 798 - 802. ISSN 1549-7747

Dimensions Badge

Altmetric Badge

Item type Article
URI https://vuir.vu.edu.au/id/eprint/33066
DOI 10.1109/TCSII.2016.2531138
Official URL http://ieeexplore.ieee.org/document/7410011/
Subjects Historical > FOR Classification > 0906 Electrical and Electronic Engineering
Current > Division/Research > College of Science and Engineering
Keywords DPLLs; UFMDPLL; incorrect noise information; signal processing; control; signals
Citations in Scopus 24 - View on Scopus
Download/View statistics View download statistics for this item

Search Google Scholar

Repository staff login

CORE (COnnecting REpositories)